Scan flip-flops are commonly used in a wide variety of circuits including application specific integrated circuits (ASIC), digital signal processors (DSP), and microprocessors, for example. In very large scale integration (VLSI) circuits, (e.g., on the scale of billions of transistors) typical designs include a significant portion of scan flip-flops (e.g., scan registers, scan master/slave latches) for test and verification. However, scan flip-flops are among the largest cells (as compared to other flip-flops, for example) because the functionality requires a larger number of transistors. Scan flip-flops require a larger surface area of the silicon due to the larger number of transistors required in a scan flip-flop, and often results in routing congestion in dense portions of instantiated scan flip-flops. Furthermore, the gates of a significant portion of the transistors in a scan flip-flop are coupled to a clock signal. Scan flip-flops normally consume more power, due to the large number of gates in a scan flip-flop that are coupled to the clock.
Scan flip-flops with asynchronous reset require even more transistors than a non-resettable scan flip-flop. As process technology rules trend toward more aggressive design rules at each successively smaller technology steps (e.g., routing in polysilicon layers drawn using 28 nm or 20 nm technologies), it is increasingly more difficult to layout the scan flip-flops because of the considerable size and power penalties of using resettable scan flip-flops.